Publications

2016

• SPACIROC3: A low power 100MHz photon counting ASIC for cosmic ray observatory
  
  • Blin S
  • Dulucq F
  • Thienpont D
  • de La Taille C
  • Miyamoto H
  , 2016. SPACIROC (Spatial Photomultiplier Array Counting and Integrating ReadOut Chip) is the front-end ASIC designed for the space-borne fluorescent telescope JEM-EUSO (Extreme Universe Space Observatory onboard Japanese Experiment Module). This ASIC is dedicated to readout 64-channel Multi-Anode Photo-Multiplier Tube (MAPMT). The two main features are the photon counting for each input and the charge conversion for each 8-channel sum. In the photon counting mode, 100% trigger efficiency is achieved for 1/3 photo-electron (p.e.) input charges. In order to avoid pile-up in the case of a large flux of photons, the double pulse separation must be shorter than 10 ns. The high-speed performance is obtained with a low power consumption (1 mW/channel) thanks to the SiGe technology and by integrating photo-electron trigger counters and a dedicated design to improve the double pulse separation up to 100 MHz. For the charge measurement, the ASIC should operate with a large dynamic range (1 p.e. to 100 p.e. per pixel). SPACIROC3 has been designed to improve the double pulse resolution compared to the previous version, which was extensively used in the EUSO balloon campaign of 2014. The architecture and the performance of the photon counting part will be detailed in this presentation. (10.1109/nssmic.2016.8069884)
  DOI : 10.1109/nssmic.2016.8069884
• LAUROC: 'A new electronically cooled line-terminating preamplifier for the ATLAS liquid argon calorimeter upgrade
  
  • Dulucq F.
  • de La Taille C.
  • Martin-Chassard G.
  • Seguin-Moreau N.
  • Duflot L.
  • Morange N.
  • Serin L.
  • Simion S.
  , 2016, pp.8069900. The readout electronics of the ATLAS Liquid Argon (LAr) Calorimeter (for the phase II of the high luminosity Large Hadron Collider at CERN) will be replaced and integrated in a single chip in order to reduce the power dissipation by an order of magnitude and to provide fully digital data. The cornerstone of the circuit is the preamplifier which is very demanding in terms of low noise, large dynamic range (at least 16 bits) and precise input impedance (25 or 50 Ohms) to terminate the cables from the detector. An innovative architecture is proposed to fulfill these requirements: a current conveyer and a single resistor are imbedded as feedback of a low noise amplifier. This architecture ensures accurate input impedance over a large frequency range (100MHz) as well as input current range (10mA). The noise remains low thanks to this architecture which acts as an “electronically cooled” resistor out of an ultra-low noise amplifier (0.4 n V / √Hz). This design provides at the same time a current and a voltage output which could be used as high and low gain paths. An anti-saturation system is embedded to switch off the high gain when is saturated. “LAUROC”, which stands for Liquid Argon Upgrade Read-Out Chip, represents the first step of this new chip development designed in TSMC 130nm technology by OMEGA. The chip was sent in fabrication in April and is expected during summer to be tested in laboratory on a test board developed by LAL group. (10.1109/NSSMIC.2016.8069900)
  DOI : 10.1109/NSSMIC.2016.8069900
• Implementation of the first level trigger for ultra-high-energy cosmic ray (UHECR) detection from space with JEM-EUSO: Initial test results
  
  • Jung A.
  • Bacholle S.
  • Barrillon P.
  • Bayer J.
  • Bertaina M.
  • Blin-Bondil S.
  • Cambursano S.
  • Casolino M.
  • Contino G.
  • Cotto G.
  • Cummings A.
  • Dagoret-Campagne S.
  • Eser J.
  • Fenu F.
  • Fornaro C.
  • Forza R.
  • Gorodetzky P.
  • Gregg R.
  • Hunt P.
  • Kawasaki Y.
  • Krantz H.
  • Larsson O.
  • Manfrin M.
  • Mignone M.
  • Miyamoto H.
  • Osteria G.
  • Parizot E.
  • Piotrowski L.W.
  • Perfetto F.
  • Prevot G.
  • Rabanal J.
  • Rezazadeh M.
  • Suino G.
  • Wiencke L.
  , 2016, pp.8069847. The JEM-EUSO Collaboration aims to study Ultra-High-Energy Cosmic Ray (UHECR) using a novel approach of looking down from space and using the atmosphere as a large detector to achieve a large effective area and therefore high-statistics on these events for the first time. For this purpose we have been developing a series of pathfinders operating from the ground, high altitude balloons and space, all sharing the same electronics, in particular the central data acquisition system. We report on the implementation and successful testing of the first-level trigger (L1) within the FPGA of the photo-detection module (PDM) board, which processes the signals from 36 64-pixel MAPMTs with a time unit of 2.5 μs to detect the passage of light from cosmic ray generated air-showers. (10.1109/NSSMIC.2016.8069847)
  DOI : 10.1109/NSSMIC.2016.8069847
• SKIROC2_CMS an ASIC for testing CMS HGCAL
  
  • Borg J.
  • Callier S.
  • Coko D.
  • Dulucq F.
  • de La Taille C.
  • Raux L.
  • Sculac T.
  • Thienpont D.
  , 2017, 12 (02), pp.C02019. SKIROC2_CMS is a chip derived from CALICE SKIROC2 that provides 64 channels of low noise charge preamplifiers optimized for 50 pF pin diodes and 10 pC dynamic range. They are followed by high gain and low gain 25 ns shapers, a 13-deep 40 MHz analog memory used as a waveform sampler at 40 MHz. and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA techniques at system level and in test-beam. The chip was sent to fabrication in January 2016 in AMS SiGe 0,35 μm and was received in May. It was tested in the lab during the summer and will be mounted on sensors for beam-tests in the fall. (10.1088/1748-0221/12/02/C02019)
  DOI : 10.1088/1748-0221/12/02/C02019
• Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays
  
  • Blin S.
  • Callier S.
  • Conforti Di Lorenzo S.
  • Dulucq F.
  • de La Taille C.
  • Martin-Chassard G.
  • Seguin-Moreau N.
  , 2017, 12 (03), pp.C03041. CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper. (10.1088/1748-0221/12/03/C03041)
  DOI : 10.1088/1748-0221/12/03/C03041